1. Field of the Invention
The present invention relates to a transmission system using a subordinate synchronization method, and in particular, to a transmission system including multistage reproduction nodes capable of suppressing accumulation of alignment jitter which directly exerts influence upon occurrence of data errors.
2. Description of the Related Art
In a transmission system constituted of a plurality of reproduction nodes connected in series to each other via a transmission path in which each node includes a timing extraction circuit for extracting a timing signal from an input signal received from the transmission path and a logic circuit (digital signal circuit) for converting the input signal into a digital signal according to the timing (clock) signal extracted by the timing extraction circuit, communicating the digital signal with a terminal (data processor) connected thereto, and transmitting the digital signal to a subsequent node, there has been an essential technological problem of suppressing accumulation of jitter.
Prior technologies related to this problem are as follows, for example.
(1) In the JP-A-61-182343, there has been proposed a transmission system in which a delay element having a delay time equal to a delay time taking place in the digital signal circuit (to be referred to as a logical delay time in this specification herebelow) is inserted in the timing system of each node, thereby suppressing accumulation of alignment jitter which is a relative jitter between the jitter of the received signal and that of the clock signal. PA1 (2) The JP-62-243449 has proposed a multistage repeater using a phase-locked loop (PLL) in the timing extraction circuit in which the circuit designing is conducted to prevent a response delay time .tau. of the PLL from being coincident with a delay time t occurring in the logic circuit, thereby implementing a transmission system preventing the accumulation of alignment jitter. PA1 (3) In the JP-A-50-132809 and JP-A-52-56810, there has been proposed an idea in which intervals between input and output electrodes formed in a comb shape in a surface acoustic wave (SAW) filter employed as a timing extraction filter are designed so as to increase a propagation path of the surface acoustic wave to develop a fixed signal delay, thereby suppressing accumulation of systematic jitter.
In the actual application, however, it is difficult to set the delay value of the delay element inserted in the timing extraction circuit of each node to be completely equal to the value of the delay time of the logic circuit as proposed in the prior art (1) above. Moreover, it is quite inconvenient for the production of the node device to adjust, each time the signal delay quantity of the logic circuit is altered due to the modification in the design of nodes, the delay time of the timing extraction circuit to match the logical delay.
In general, since the logical delay time cannot be easily reduced to an arbitrary value, in the conventional technology (2) in which the logic delay is prevented from being coincident with the response delay of the PLL to suppress accumulation of alignment jitter, there is adopted a method in which delay means is inserted in the logic circuit to increase the logic delay time or a method in which the filter characteristic Q of the timing extraction circuit is changed to shift the response delay time of the PLL. In this case, a value (to be referred to as an equivalent logical delay herebelow) obtained by subtracting the delay quantity of the timing extraction circuit from the logical delay time becomes to be positive.
According to the prior art (2) above, however, a problem appears in the system designing stage as follows. Namely, when the logical delay quantity is increased for the suppression of jitter, the signal transmission delay becomes to be greater in the entire repeater system. On the other hand, when the filter characteristic Q is increased, the response time constant of the timing system is also becomes to be larger. Consequently, the follow-up characteristic of the signal response is deteriorated and the characteristic of phase change with respect to temperature also becomes to be worse. Conversely, when the value Q is minimized, the system becomes to be easily influenced from noises outside the base band, which causes a wrong tuning and an increase in random jitter.
That is, according to the prior art (2), to suppress accumulation of alignment jitter, it is necessary to greatly alter designing parameters such as the value Q of the timing extraction circuit and the delay quantity of the logic circuit. This leads to a problem that characteristics of the respective circuits cannot be easily optimized. Furthermore, in the conventional technology above, there has not been clearly described any guideline for values of the designing parameters to suppress the accumulation of jitter to the minimum value. Consequently, each designer is required to experimentally find out parameters which effectively suppress alignment jitter.
In accordance with the prior art (3), since a fixed delay value is used for each SAW filter, when the delay quantity of the logic circuit is altered for some reasons such as a change of designing thereof, a new designing of the SAW filter is required to suppress the accumulation of jitter. In this connection, since the object of the invention (3) is to suppress accumulation of systematic jitter, accumulation of alignment jitter due to the logical delay and relationships between the fixed delay quantity and the logical delay quantity for suppression thereof have not been fully discussed.